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LTC1857/LTC1858/LTC1859 8-Channel, 12-/14-/16-Bit, 100ksps SoftSpan A/D Converters with Shutdown
FEATURES

DESCRIPTIO

Sample Rate: 100ksps 8-Channel Multiplexer with 25V Protection Single 5V Supply Software-Programmable Input Ranges: 0V to 5V, 0V to 10V, 5V or 10V Single Ended or Differential 3LSB INL for the LTC1859, 1.5LSB INL for the LTC1858, 1LSB INL for the LTC1857 Power Dissipation: 40mW (Typ) SPI/MICROWIRETM Compatible Serial I/O Power Shutdown: Nap and Sleep Signal-to-Noise Ratio: 87dB (Typ) for the LTC1859 Operates with Internal or External Reference Internal Synchronized Clock 28-Pin SSOP Package
The LTC(R)1857/LTC1858/LTC1859 are 8-channel, low power, 12-/14-/16-bit, 100ksps, analog-to-digital converters (ADCs). These SoftSpanTM ADCs can be softwareprogrammed for 0V to 5V, 0V to 10V, 5V or 10V input spans and operate from a single 5V supply. The 8-channel multiplexer can be programmed for single-ended inputs or pairs of differential inputs or combinations of both. In addition, all channels are fault protected to 25V. A fault condition on any channel will not affect the conversion result of the selected channel. An onboard high performance sample-and-hold and precision reference minimize external components. The low 40mW power dissipation is made even more attractive with two user selectable power shutdown modes. DC specifications include 3LSB INL for the LTC1859, 1.5LSB INL for the LTC1858 and 1LSB for the LTC1857. The internal clock is trimmed for 5s maximum conversion time and the sampling rate is guaranteed at 100ksps. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S

Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing
TYPICAL APPLICATIO
100kHz, 12-Bit/14-Bit/16-Bit Sampling ADC
CONVST COM CH0 LTC1857/ RD CH1 LTC1858/ SCK CH2 LTC1859 SDI DGND CH3 SDO CH4 BUSY CH5 OVDD CH6 DVDD CH7 AVDD MUXOUT + MUXOUT - AGND3 ADC+ AGND2 ADC- REFCOMP AGND1 VREF
2.0 1.5
SOFTWARE-PROGRAMMABLE SINGLE-ENDED OR DIFFERENTIAL INPUTS (0V TO 5V, 0V TO 10V, 5V OR 10V)
P CONTROL LINES
INL (LSB)
10F
10F
3V TO 5V 5V 5V 10F
2.5V 1F 10F
U
LTC1859 Typical INL Curve
1.0 0.5 0 - 0.5 -1.0 -1.5 -2.0 -32768 -16384 0 CODE 16384 32767
1859 TA02
U
U
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LTC1857/LTC1858/LTC1859 ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW COM CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 9 28 CONVST 27 RD 26 SCK 25 SDI 24 DGND 23 SDO 22 BUSY 21 OVDD 20 DVDD 19 AVDD 18 AGND3 17 AGND2 16 REFCOMP 15 VREF
Supply Voltage (OVDD = DVDD = AVDD = VDD) ........... 6V Ground Voltage Difference DGND, AGND1, AGND2, AGND3 ...................... 0.3V Analog Input Voltage ADC+, ADC- (Note 3) ...................(AGND1 - 0.3V) to (AVDD + 0.3V) CH0-CH7, COM .................................................. 25V Digital Input Voltage (Note 4) ...... (DGND - 0.3V) to 10V Digital Output Voltage .... (DGND - 0.3V) to (DVDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1857C/LTC1858C/LTC1859C ............ 0C to 70C LTC1857I/LTC1858I/LTC1859I .......... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec) ................. 300C
ORDER PART NUMBER LTC1857CG LTC1857IG LTC1858CG LTC1858IG LTC1859CG LTC1859IG
MUXOUT + 10 MUXOUT - 11 ADC + 12 ADC - 13 AGND1 14
G PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 95C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER A D
PARAMETER Resolution No Missing Codes Transition Noise Integral Linearity Error Differential Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Bipolar Zero Error Match Unipolar Zero Error Unipolar Zero Error Drift Unipolar Zero Error Match Bipolar Full-Scale Error Bipolar Full-Scale Error Drift Bipolar Full-Scale Error Match Unipolar Full-Scale Error Unipolar Full-Scale Error Drift Unipolar Full-Scale Error Match Input Common Mode Range
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. MUXOUT connected to ADC inputs. (Notes 5, 6)
CONDITIONS

ULTIPLEXER CHARACTERISTICS
MIN 12 12 LTC1857 TYP MAX MIN 14 14
LTC1858 TYP MAX
MIN 16 15
LTC1859 TYP MAX
0.06 (Notes 7, 15) (Note 15) (Note 8)

0.26 1 1 9 -1 0.1 4 6 6 15 1 1.2 0.35 0.45 2 0.15 0.40 2.5 7 5 0.45 0.75 10 0.25 0.85 2.5 7 5 12 0 to 10 10 96 1.5 1.5 17 -2
1 3 4 28 0.1 10 25 1 8 0.1 0.4 2.5 7 15 0.20 0.75 2.5 7 15 0 to 10 10 96
-1 0.1
(Note 8)
1 External Reference (Note 11) Internal Reference (Note 11) External Reference Internal Reference External Reference (Note 11) Internal Reference (Note 11) External Reference Internal Reference Unipolar Mode Bipolar Mode

2.5 7
2.5 7 0 to 10 10 96
Input Common Mode Rejection Ratio
UNITS Bits Bits LSBRMS LSB LSB LSB ppm/C LSB LSB ppm/C LSB % % ppm/C ppm/C LSB % % ppm/C ppm/C LSB V V dB
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2
U
W
U
U
WW
WU
W
U
LTC1857/LTC1858/LTC1859
A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25C. (Note 5)
PARAMETER Analog Input Range CONDITIONS CH0 to CH7, COM ADC+, ADC- (Note 3) MIN TYP 0 to 5, 0 to 10 5, 10 0 to 2.048 0 to 4.096 ADC - 1.024 ADC - 2.048 42 31 10 5 Hi-Z 5 24 12 4
Impedance
Capacitance
Input Leakage Current
DY A IC ACCURACY
SYMBOL THD PARAMETER Total Harmonic Distortion
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. MUXOUT connected to ADC inputs. (Notes 5 and 12)
CONDITIONS 1kHz Input Signal, First Five Harmonics 1kHz Input Signal 1kHz Input Signal MIN LTC1857 TYP MAX 74 -101 -103 -120 1 -70 60 Full-Scale Step (Note 9) (Note 13) 150 4 150 MIN LTC1858 TYP MAX 83 -101 -103 -120 1 -70 60 4 150 MIN LTC1859 TYP MAX 87 -101 -103 -120 1 -70 60 4 UNITS dB dB dB dB MHz ns ps s ns
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal
Peak Harmonic or Spurious Noise Channel-to-Channel Isolation -3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery
U
WU
U
MAX
UNITS V V V V V V k k k k k pF pF pF pF
CH0 to CH7, COM Unipolar Bipolar MUXOUT+ , MUXOUT- Unipolar Bipolar ADC+, ADC- CH0 to CH7, COM Sample Mode ADC+, ADC- 0V to 2.048V, 1.024V 0V to 4.096V, 2.048V Hold Mode ADC+, ADC- ADC+, ADC-, CONVST = Low
1
A
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LTC1857/LTC1858/LTC1859
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
PARAMETER VREF Output Voltage VREF Output Temperature Coefficient VREF Output Impedance VREFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 -0.1mA IOUT 0.1mA IOUT = 0
I TER AL REFERE CE CHARACTERISTICS
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN

POWER REQUIRE E TS
PARAMETER Positive Supply Voltage Positive Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Notes 9 and 10)
4
UW
U
U
U
U
U
MIN 2.475
TYP 2.50 10 8 4.096
MAX 2.525
UNITS V ppm/C k V
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
5 VDD = 4.75V, IO = -10A, OVDD = VDD VDD = 4.75V, IO = -200A, OVDD = VDD VDD = 4.75V, IO = 160A, OVDD = VDD VDD = 4.75V, IO = 1.6mA, OVDD = VDD VOUT = 0V to VDD, RD = High RD = High VOUT = 0V VOUT = VDD 4.74

4 0.05 0.10 15 -10 10 0.4 10
V V A pF mA mA
MIN 4.75
TYP 5.00 8.0 5.5 8.0 40.0 27.5 40.0
MAX 5.25 13 8 15
UNITS V mA mA A mW mW W
CONVST = 0V or 5V
CONVST = 0V or 5V
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LTC1857/LTC1858/LTC1859 TI I G CHARACTERISTICS
SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency tCONV tACQ fSCK tr tf t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Conversion Time Acquisition Time SCK Frequency SDO Rise Time SDO Fall Time CONVST High Time CONVST to BUSY Delay SCK Period SCK High SCK Low Delay Time, SCK to SDO Valid Time from Previous SDO Data Remains Valid After SCK SDO Valid After RD RD to SCK Setup Time SDI Setup Time Before SCK SDI Hold Time After SCK SDO Valid Before BUSY Bus Relinquish Time RD = Low, CL = 25pF, See Test Circuits See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits Through CH0 to CH7 Inputs Through ADC+ , ADC- Only (Note 14) See Test Circuits See Test Circuits

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS Through CH0 to CH7 Inputs Through ADC+ , ADC- Only

Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1, AGND2 and AGND3 wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above AVDD = DVDD = OVDD = VDD, they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended analog MUX input with respect to ground or ADC+ with respect to ADC- tied to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band.
UW
MIN 100
TYP 166 4 1
MAX
UNITS kHz kHz
5 4
s s s MHz ns ns ns
0 6 6 40 15 50 10 10 25 5 20 11 20 0 7 5 20 10
20
30
ns ns ns ns
45
ns ns
30
ns ns ns ns ns
30
ns
Note 8: Bipolar zero error is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11 1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage measured from 0.5LSB when the output codes flicker between 0000 0000 0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000 0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000 0000 0000 and 0000 0000 0001 for the LTC1857. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: Full-scale bipolar error is the worst case of -FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the full-scale range, and includes the effect of offset error. For unipolar full-scale error, the deviation of the last code transition from ideal, divided by the full-scale range, and includes the effect of offset error. Note 12: All Specifications in dB are referred to a full-scale 10V input. Note 13: Recovers to specified performance after (2 * FS) input overvoltage. Note 14: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns setup time for the receiving logic). Note 15: The specification is referred to the 10V input range.
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LTC1857/LTC1858/LTC1859 TYPICAL PERFOR A CE CHARACTERISTICS
LTC1859 Typical INL Curve
2.0 1.5 1.0
DNL (LSB)
INL (LSB)
0.5 0 - 0.5 -1.0 -1.5 -2.0 -32768 -16384 0 CODE 16384 32767
1859 TA02
0.5 0 - 0.5 -1.0 -1.5 -2.0 -32768 -16384 0 CODE 16384 32767
1859 G02
MAGNITUDE (dB)
LTC1859 SINAD vs Input Frequency
90 88 86 SINAD (dB) 84 82 80 78 76 74 1 10 INPUT FREQUENCY (kHz) 100
1859 G04
TOTAL HARMONIC DISTORTION (dB)
CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs)
LTC1859 Channel-to-Channel Gain Error Matching vs Temperature
1.0
INTERNAL REFERENCE VOLTAGE (V)
0.5 UNIPOLAR MODE 0
CHANGE IN REFCOMP VOLTAGE (V)
CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs)
BIPOLAR MODE
-0.5
-1.0 -50
-25
0 25 50 TEMPERATURE (C)
6
UW
75
LTC1859 Typical DNL Curve
2.0 1.5 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC1859 Nonaveraged 4096-Point FFT Plot
fSAMPLE = 100kHz fIN = 1kHz SINAD = 86.95dB THD = -101.42dB
0
5
10 15 20 25 30 35 40 45 50 FREQUENCY (kHz)
1869 G03
LTC1859 Total Harmonic Distortion vs Input Frequency
-70 1.0
LTC1859 Channel-to-Channel Offset Error Matching vs Temperature
-80
0.5 BIPOLAR MODE 0
-90
UNIPOLAR MODE
-100
-0.5
-110 1 10 INPUT FREQUENCY (kHz) 100
1859 G05
-1.0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1959 G06
Internal Reference Voltage vs Temperature
2.520 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 -50 -25 50 25 TEMPERATURE (C) 0 75 100
1859 G08
Change in REFCOMP Voltage vs Load Current
0.04
0.02
0
-0.02
100
1959 G07
-0.04 -50
-40
-30 -20 -10 LOAD CURRENT (mA)
0
10
1859 G09
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LTC1857/LTC1858/LTC1859 TYPICAL PERFOR A CE CHARACTERISTICS
LTC1859 Power Supply Feedthrough vs Ripple Frequency
-10
POWER SUPPLY FEEDTHROUGH (dB)
-30 -40 -50 -60 -70 -80 100
SUPPLY CURRENT (mA)
8.5
POSITIVE SUPPLY CURRENT (mA)
-20
fSAMPLE = 100kHz VRIPPLE = 60mV
1k 10k 100k RIPPLE FREQUENCY (Hz)
PI FU CTIO S
COM (Pin 1): Common Input. This is the reference point for all single-ended inputs. It must be free of noise and is usually connected to the analog ground plane. CH0 (Pin 2): Analog MUX Input. CH1 (Pin 3): Analog MUX Input. CH2 (Pin 4): Analog MUX Input. CH3 (Pin 5): Analog MUX Input. CH4 (Pin 6): Analog MUX Input. CH5 (Pin 7): Analog MUX Input. CH6 (Pin 8): Analog MUX Input. CH7 (Pin 9): Analog MUX Input. MUXOUT + (Pin 10): Positive MUX Output. Output of the analog multiplexer. Connect to ADC + for normal operation. MUXOUT - (Pin 11): Negative MUX Output. Output of the analog multiplexer. Connect to ADC - for normal operation. ADC + (Pin 12): Positive Analog Input to the Analog-toDigital Converter. ADC - (Pin 13): Negative Analog Input to the Analog-toDigital Converter. AGND1 (Pin 14): Analog Ground. VREF (Pin 15): 2.5V Reference Output. Bypass to analog ground with a 1F tantalum capacitor. REFCOMP (Pin 16): Reference Buffer Output. Bypass to analog ground with a 10F tantalum and a 0.1F ceramic capacitor. Nominal output voltage is 4.096V. AGND2 (Pin 17): Analog Ground. AGND3 (Pin 18): Analog Ground. This is the substrate connection. AVDD (Pin 19): 5V Analog Supply. Bypass to analog ground with a 0.1F ceramic and a 10F tantalum capacitor. DVDD (Pin 20): 5V Digital Supply. Bypass to digital ground with a 0.1F ceramic and a 10F tantalum capacitor. OVDD (Pin 21): Positive Supply for the Digital Output Buffers (3V to 5V). Bypass to digital ground with a 0.1F ceramic and a 10F tantalum capacitor. BUSY (Pin 22): Output shows converter status. It is low when a conversion is in progress. SDO (Pin 23): Serial Data Output.
UW
1859 G10
Supply Current vs Supply Voltage
9.0 fSAMPLE = 100kHz
Supply Current vs Temperature
9.0 fSAMPLE = 100kHz
8.5
8.0
8.0
7.5
7.5
1M
7.0 4.5
5 5.25 4.75 SUPPLY VOLTAGE (V)
5.5
1859 G11
7.0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1859 G12
U
U
U
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LTC1857/LTC1858/LTC1859
PI FU CTIO S
DGND (Pin 24): Digital Ground. SDI (Pin 25): Serial Data Input. SCK (Pin 26): Serial Data Clock. RD (Pin 27): Read Input. This active low signal enables the digital output pin SDO. CONVST (Pin 28): Conversion Start. This active high signal starts a conversion on its rising edge.
FU CTIO AL BLOCK DIAGRA
CH0 CH1
* * *
INPUT MUX AND RANGE SELECT
CH7 COM
MUXOUT- AGND1
MUXOUT+
ADC+
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DN 1k 25pF DN 25pF DN 1k 25pF DN 25pF
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1859 TC01
8
W
U
U
U
U
U
AVDD
DVDD
MUX ADDRESS AND RANGE CONTROL LOGIC INTERNAL CLOCK
CONVST SDI BUSY
SCK
+
12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O RD OVDD SDO 4.096V 2.5V REFERENCE 1.6384X
-
8k
ADC- VREF REFCOMP
1859 BD
AGND2 AGND3 DGND
Load Circuits for Output Float Delay
5V 1k
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1859 TC02
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LTC1857/LTC1858/LTC1859
TI I G DIAGRA S
t 2 (CONVST to BUSY Delay)
t2 2.4V
t1 (For Short Pulse Mode)
t1 CONVST 50% 50%
1859 TD01
t3, t4, t5 (SCK Timing)
SCK
t4 SCK t5
t8 (SDO Valid After RD)
t8 RD
0.4V
SDO
Hi-Z
t 10 (SDI Setup Time Before SCK)
t10 SCK 2.4V
SCK
SDI
2.4V 0.4V
1859 TD07
t 12 (SDO Valid Before BUSY, RD = 0)
t12 BUSY 2.4V
SDO
2.4V
W
UW
CONVST
BUSY
0.4V
1859 TD02
t 6 (Delay Time, SCK to SDO Valid) t7 (Time from Previous Data Remains Valid After SCK)
t6 t7 0.4V
SDO
t3
1859 TD03
2.4V 0.4V
1859 TD04
t9 (RD to SCK Setup Time)
t9 RD 0.4V
2.4V 0.4V
1859 TD05
SCK
2.4V
1959 TD06
t11 (SDI Hold Time After SCK)
t11 2.4V
SDI
2.4V 0.4V
1859 TD08
t 13 (BUS Relinquish Time)
t13 RD 2.4V
B15
1859 TD09
SDO
90% 10%
Hi-Z
1859 TD10
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
OVERVIEW The LTC1857/LTC1858/LTC1859 are innovative, multichannel ADCs that provide software-selectable input ranges for each of their eight input channels. Using on-chip resistors and switches, it provides an attenuation and offset that can be programmed for each channel on the fly. The precisely trimmed attenuators ensure accurate input ranges. Because they precede the multiplexer, errors due to multiplexer on-resistance are eliminated. The input word that selects the input channel also selects the desired input range for that channel. The available ranges are 0V to 5V, 0V to 10V (unipolar), 5V and 10V (bipolar). They are achieved with the ADC running on a single 5V supply. In addition to the range selection, single ended or differential inputs may be selected for each channel or pair of channels. Finally, overrange protection is provided for unselected channels. An overrange condition on an unused channel will not affect the conversion result on the selected channel. CONVERSION DETAILS The LTC1857/LTC1858/LTC1859 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-/14-/16-bit serial output respectively. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) The analog signals applied at the MUX input channels are rescaled by the resistor divider network formed by R1, R2 and R3 as shown below. The rescaled signals appear on the MUXOUT (Pins 10, 11) which are also connected to the ADC inputs (Pins 12, 13) under normal operation.
REFCOMP BIPOLAR R1 25k R3 10k CH SEL MUXOUT R2 17k
1859 AI03
MUX INPUT
10
U
Before starting a conversion, an 8-bit data word is clocked into the SDI input on the first eight rising SCK edges to select the MUX address, input range and power down mode. The ADC enters acquisition mode on the falling edge of the sixth clock in the 8-bit data word and ends on the rising edge of the CONVST signal which also starts a conversion (see Figure 7). A minimum time of 4s will provide enough time for the sample-and-hold capacitors to acquire the analog signal. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 12-/14-/ 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a high speed comparator. At the end of a conversion, the DAC output balances the analog input (ADC + - ADC -). The SAR contents (a 16-bit data word) which represents the difference of ADC+ and ADC- are loaded into the 12-/14-/16-bit shift register. DRIVING THE ANALOG INPUTS The nominal input ranges for the LTC1857/LTC1858/ LTC1859 are 0V to 5V, 0V to 10V, 5V and 10V and the MUX inputs are overvoltage protected to 25V. The input impedance is typically 42k in unipolar mode and 31k in bipolar mode, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 3000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1857/LTC1858/ LTC1859. More detailed information is available in the Linear Technology data books and online at www.linear.com. LT(R)1007: Low noise precision amplifier. 2.7mA supply current 5V to 15V supplies. Gain bandwidth product 8MHz. DC applications.
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W
UU
LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO U
AVDD DVDD MUX ADDRESS AND RANGE CONTROL LOGIC INPUT MUX AND RANGE SELECT INTERNAL CLOCK CONVST SDI BUSY SCK
CH0 CH1
* * *
CH7 COM
MUXOUT- AGND1
Figure 1. LTC1857/LTC1858/LTC1859 Simplified Equivalent Circuit
AIN+ 3000pF AIN- CH1 * * * * MUXOUT+ MUXOUT- ADC+ ADC-
1859 F02
CH0
Figure 2. Analog Input Filtering
LT1227: 140MHz video current feedback amplifier. 10mA supply current. 5V to 15V supplies. Low noise and low distortion. LT1468/LT1469: Single and dual 90MHz, 16-bit accurate op amp. Good AC/DC specs. LT1677: Single, low noise op amp. Rail-to-rail input and output. Up to 15V supplies.
W
UU
+
12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O RD OVDD SDO 4.096V 2.5V REFERENCE 1.6384X
-
8k
MUXOUT+
ADC+
ADC- VREF REFCOMP
1859 BD
AGND2 AGND3 DGND
LT1792: Single, low noise JFET input op amp, 5V supplies. LT1793: Single, low noise JFET input op amp, 10pA bias current, 5V supplies. LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps. Up to 15V supplies. LT1844/LT1885: Dual and quad, 400pA bias current, railto-rail output op amps. Up to 15V supplies. Faster response and settling time. INTERNAL VOLTAGE REFERENCE The LTC1857/LTC1858/LTC1859 have an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the LTC1857/LTC1858/LTC1859 is equal to 5V, 0V to 5V, 10V or 0V to 10V. The output of the reference is connected to the input of a gain of 1.6384x buffer through an 8k resistor (see Figure 3). The input to the
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
buffer or the output of the reference is available at VREF (Pin 15). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at REFCOMP (Pin 16). The REFCOMP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade.
8k
2.5V
15 VREF 1F
2.5V REFERENCE
12-/14-/16-BIT CAPACITIVE DAC
4.096V 0.1F
1.6384X BUFFER 16 REFCOMP
1859 F03
10F
Figure 3. Internal or External Reference Source
For minimum code transition noise the VREF pin and the REFCOMP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer. UNIPOLAR / BIPOLAR OPERATION Figure 4a shows the ideal input/output characteristics for the LTC1859. The code transitions occur midway between
FS 65536
111...111 111...110 111...101
1LSB =
OUTPUT CODE
OUTPUT CODE
111...100
000...011 000...010 000...001 000...000 0V
UNIPOLAR ZERO
1 LSB INPUT VOLTAGE (V)
FS - 1LSB
1859 F4a
Figure 4a. Unipolar Transfer Characteristics (UNI = 1)
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successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS - 1.5LSB). The output code is natural binary with 1LSB = FS/65536. Figure 4b shows the input/output transfer characteristics for the bipolar mode in two's complement format. FULL SCALE AND OFFSET In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. Offset error must be adjusted before full-scale error. Zero offset is achieved by adjusting the offset applied to the "-" input. For single-ended inputs, this offset should be applied to the COM pin. For differential inputs, the "-" input is dictated by the MUX address. For unipolar zero offset error, apply 0.5LSB (actual voltage will vary with input span selected) to the "+" input and adjust the offset at the "-" input until the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000 0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000 0000 0000 and 0000 0000 0001 for the LTC1857. For bipolar zero error, apply - 0.5LSB (actual voltage will vary with input span selected) to the "+" input and adjust the offset at the "-" input until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and
011...111 011...110 1LSB = FS 65536 BIPOLAR ZERO 000...001 000...000 111...111 111...110 100...001 100...000 -FS/2 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
1859 F4b
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Figure 4b. Bipolar Transfer Characteristics (UNI = 0)
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
11 1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111 1111 1111 for the LTC1857. As mentioned earlier, the internal reference is factory trimmed to 2.50V. To make sure that the reference buffer gain is not compensating for trim errors in the reference, REFCOMP is trimmed with an accurate external 2.5V reference applied to VREF. For unipolar inputs, an input voltage of FS - 1.5LSBs should be applied to the "+" input and the appropriate reference adjusted until the output code flickers between 1111 1111 1111 1110 and 1111 1111 1111 1111 for the LTC1859, between 11 1111 1111 1110 and 11 1111 1111 1111 for the LTC1858 and between 1111 1111 1110 and 1111 1111 1111 for the LTC1857. For bipolar inputs, an input voltage of FS - 1.5LSBs should be applied to the "+" input and the appropriate reference adjusted until the output code flickers between 0111 1111 1111 1110 and 0111 1111 1111 1111 for the LTC1859, between 01 1111 1111 1110 and 01 1111 1111 1111 for the LTC1858 and between 0111 1111 1110 and 0111 1111 1111 for the LTC1857. These adjustments as well as the factory trims affect all channels. The channel-to-channel offset and gain error matching are guaranteed by design to meet the specifications in the Converter Characteristics table. DC PERFORMANCE One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the MUX and the resulting output codes are collected over a large number of conversions. For example in Figure 5 the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 1LSB for the LTC1859. DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 4s. No external adjustments are required and, with the maximum acquisition time of 4s, throughput performance of 100ksps is assured.
COUNT
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1800 1600 1400 1200 1000 800 600 400 200 0 -4 -3 -2 -1 1 0 CODE 2 3 4
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Figure 5. LTC1859 Histogram for 4096 Conversions
3V Input/Output Compatible The LTC1857/LTC1858/LTC1859 operate on a 5V supply, which makes the devices easy to interface to 5V digital systems. These devices can also interface to 3V digital systems: the digital input pins (SCK, SDI, CONVST and RD) of the LTC1857/LTC1858/LTC1859 recognize 3V or 5V inputs. The LTC1857/LTC1858/LTC1859 have a dedicated output supply pin (OVP) that controls the output swings of the digital output pins (SDO, BUSY) and allows the part to interface to either 3V or 5V digital systems. The output is two's complement binary for bipolar mode and offset binary for unipolar mode. Timing and Control Conversion start and data read are controlled by two digital inputs: CONVST and RD. To start a conversion and put the sample-and-hold into the hold mode bring CONVST high for no less than 40ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. Figures 6a and 6b show two different modes of operation for the LTC1859. For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively. In mode 1 (Figure 6a), RD is tied low. The rising edge of CONVST starts the conversion. The data outputs are always enabled. The MSB of the data output is available after the conversion. In mode 2 (Figure 6b), CONVST and RD are tied together. The rising edge of the CONVST signal starts the conversion. Data outputs are in
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RD = 0
t2
BUSY tCONV
1859 F06a
t9
t3
t13
APPLICATIO S I FOR ATIO
CONVST = RD
LTC1857/LTC1858/LTC1859
t4 1 4 5 6 7 8 15 16 2 3 4 5 1
2
3
6
7
8
15
16
SCK tACQ UNI GAIN NAP SLEEP DON'T CARE t7 Hi-Z B11 B10 B9 B8 B1 B0 (LSB) t2 B15 (MSB) B14 B13 t6 SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 UNI GAIN NAP SLEEP DON'T CARE
t10
t11
SDI
DON'T CARE
SGL/ DIFF
ODD/ SIGN
SELECT 1
SELECT 0
SHIFT CONFIGURATION WORD IN B12
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B12 B11 B10 B9 B8 B1 B0 (LSB) Hi-Z
SDO
Hi-Z
B15 (MSB)
B14
B13
t8
BUSY tCONV
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Figure 6b. Mode 2 for the LTC1859*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
t13
t9
t3
RD
t4 1 4 5 6 7 8 15 16
t5 1 2 3 4 5 6 7 8 15 16
2
3
SCK tACQ UNI GAIN NAP SLEEP DON'T CARE t7 B9 B8 B1 t6 Hi-Z B11 B10 B0 (LSB) t1 B15 (MSB) B14 SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 UNI GAIN NAP SLEEP SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 B1 B0 (LSB) Hi-Z DON'T CARE
t10
t11
SDI
DON'T CARE
SGL/ DIFF
ODD/ SIGN
SELECT 1
SELECT 0
SHIFT CONFIGURATION WORD IN
SDO
Hi-Z
B15 (MSB)
B14
B13
B12
t8
CONVST t2
BUSY tCONV
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Figure 7. Operating Sequence for the LTC1859*
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
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t5
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Figure 6a. Mode 1 for the LTC1859*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
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B0 (LSB)
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4 5 6 7 8 15 16 1 2 3 4 5 6 7 8 15 16 tACQ UNI GAIN NAP SLEEP DON'T CARE UNI GAIN NAP SLEEP DON'T CARE t7 B9 B8 B1 B0 (LSB) B11 B10 B9 B8 B1 t1 t12 B15 (MSB) B14 B13 B12 t6 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 B12 B11 B10
t3
t5
t4 1
2
3
SCK
t10
t11
SDI
DON'T CARE
SGL/ DIFF
ODD/ SIGN
SELECT 1
SELECT 0
SHIFT CONFIGURATION WORD IN
SDO
B15 (MSB)
B14
B13
t12
CONVST
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
three-state at this time. When the conversion is complete (BUSY goes high), CONVST and RD go low to enable the data output for the previous conversion. SERIAL DATA INPUT (SDI) INTERFACE The LTC1857/LTC1858/LTC1859 communicate with microprocessors and other external circuitry via a synchronous, full duplex, 3-wire serial interface (see Figure 7). The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). An 8-bit input word is shifted into the SDI input which configures the LTC1857/LTC1858/LTC1859 for the next conversion. Simultaneously, the result of the previous conversion is output on the SDO line. At the end of the data exchange the requested conversion begins by applying a rising edge on CONVST. After tCONV, the conversion is complete and the results will be available on the next data
Table 1. Multiplexer Channel Selection
MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 0 0 00 0 0 01 0 0 10 0 0 11 0 1 00 0 1 01 0 1 10 0 1 11 DIFFERENTIAL CHANNEL SELECTION 0 + 1 - + - + - + - + - + - + - + - 2 3 4 5 6 7 MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 1 0 00 1 0 01 1 0 10 1 0 11 1 1 00 1 1 01 1 1 10 1 1 11 SINGLE-ENDED CHANNEL SELECTION 0 + + + + + + + + Changing the MUX Assignment "On the Fly" 1 2 3 4 5 6 7 COM - - - - - - - -
4 Differential
CHANNEL 0,1
8 Single-Ended
CHANNEL 0 1 2 3 4 5 6 7
{ { { {
2,3
+ ( -) - ( +) + ( -) - ( +) + ( -) - ( +) + ( -) - ( +)
4,5
+ + + + + + + +
COM (-)
6,7
Figure 8. Examples of Multiplexer Options on the LTC1857/LTC1858/LTC1859
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transfer cycle. As shown below, the result of a conversion is delayed by one conversion from the input word requesting it.
SDI SDO SDI WORD 1 SDO WORD 0 DATA TRANSFER tCONV A/D CONVERSION SDI WORD 2 SDO WORD 1 DATA TRANSFER tCONV A/D CONVERSION SDI WORD 3 SDO WORD 2
1859 * AI01
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INPUT DATA WORD The LTC1857/LTC1858/LTC1859 8-bit data word is clocked into the SDI input on the first eight rising SCK edges. Further inputs on the SDI pin are then ignored until the next conversion. The eight bits of the input word are defined as follows:
INPUT RANGE SGL/ DIFF ODD SIGN SELECT 1 SELECT 0 UNI GAIN NAP SLEEP
MUX ADDRESS
POWER DOWN SELECTION
1859 AI02
Combinations of Differential and Single-Ended
CHANNEL 0,1
{ {
4 5 6 7
+ - - + + + + +
COM (-) 4,5
2,3
{ {
6,7
+ - + -
COM (UNUSED) 1ST CONVERSION
4,5
{
6 7
- + + +
COM (-) 2ND CONVERSION
1859 F08
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
MUX ADDRESS
The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and - signs in the selected row of Table 1. Note that in differential mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with either polarity. In single-ended mode, all input channels are measured with respect to COM. Both the "+" and "-" inputs are sampled simultaneously so common mode noise is rejected. INPUT RANGE (UNI, GAIN) The fifth and sixth input bits (UNI, GAIN) determine the input range for the conversion. When UNI is a logical one, a unipolar conversion will be performed. When UNI is a logical zero, a bipolar conversion will result. The GAIN input bit determines the input span for the conversion. When GAIN is a logical one, either 0V to 10V or 10V input spans will be selected depending on UNI. When GAIN is a logical zero, either 0V to 5V or 5V input spans will be chosen. The input ranges for different UNI and GAIN inputs are shown in Table 2.
Table 2. Input Range Selection
UNI 0 1 0 1 GAIN 0 0 1 1 INPUT RANGE 5V 0V to 5V 10V 0V to 10V
POWER DOWN SELECTION (NAP, SLEEP) The last two bits of the input word (Nap and Sleep) determine the power shutdown mode of the LTC1857/LTC1858/ LTC1859. See Table 3. Nap mode is selected when Nap = 1 and Sleep = 0. The previous conversion result will be clocked out and a conversion will occur before entering
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the Nap mode. The Nap mode starts at the end of the conversion which is indicated by the rising edge of the BUSY signal. Nap mode lasts until the falling edge of the 2nd SCK (see Figure 9). Automatic nap will be achieved if Nap = 1 is selected each time an input word is written to the ADC.
Table 3. Power Down Selection
NAP 0 1 X SLEEP 0 0 1 POWER DOWN MODE Power On Nap Sleep
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Sleep mode will occur when Sleep = 1 is selected, regardless of the selection of the Nap input. The previous conversion result can be clocked out and the Sleep mode will start on the falling edge of the last (16th) SCK. Notice that the CONVST should stay either high or low in sleep mode (see Figure 10). To wake up from the sleep mode, apply a rising edge on the CONVST signal and then apply Sleep = 0 on the next SDI word and the part will wake up on the falling edge of the last (16th) SCK (see Figure 11). In Sleep mode, all bias currents are shut down and only the power on reset circuit and leakage currents (about 10A) remain. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 16). The wake-up time is typically 40ms with the recommended 10F capacitor connected on the REFCOMP pin. DYNAMIC PERFORMANCE FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 12 shows a typical LTC1859 FFT plot which yields a SINAD of 87dB and THD of - 101dB.
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RD
1 5 6 7 8 15 16 1 2 3 4 5 6 7 8 15 16
2
3
4
SCK
SDI SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN Hi-Z B11 B10 B9 B8 B1 B0 (LSB) B11 B10 B9 B8 B1 B0 (LSB) B15 MSB B14 B13 B12 Hi-Z
DON'T CARE UNI GAIN NAP = 1 SLEEP = 0 DON'T CARE UNI GAIN NAP SLEEP DON'T CARE SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0
SGL/ DIFF
ODD/ SIGN
SELECT 1
SELECT 0
SHIFT CONFIGURATION WORD IN
SDO
Hi-Z
B15 (MSB)
B14
B13
B12
BUSY tACQ tCONV NAP tACQ
1859 F09
RD
APPLICATIO S I FOR ATIO
1 3 4 5 6 7 8 15 16
2
SDI SHIFT WAKE-UP CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 B1 B0 (LSB) A/D RESULT NOT VALID CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE
DON'T CARE SELECT 1 SELECT 0 UNI GAIN NAP DON'T CARE
SGL/ DIFF
ODD/ SIGN
SLEEP = 0
SDO
B15 (MSB)
B14
CONVST
tCONV SLEEP
1859 F10
BUSY
Figure 10. Sleep Mode Operation for the LTC1859*
RD
1 3 4 5 6 7 8 15 16
2
1
2
3
4
5
6
7
8
15
16
SCK
SDI SHIFT WAKE-UP CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 A/D RESULT NOT VALID B1
DON'T CARE SELECT 1 SELECT 0 UNI GAIN NAP DON'T CARE
SGL/ DIFF
ODD/ SIGN
SLEEP = 0
SGL/ DIFF
ODD/ SIGN
SELECT 1
SELECT 0
UNI
GAIN
NAP
SLEEP SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B0 (LSB) B15 (MSB) B14 B13 B12 B11 B10 B9 B8
DON'T CARE
SDO
B15 (MSB)
B14
B1
B0 (LSB)
CONVST tCONV
1859 F11
tCONV
BUSY SLEEP WAKE-UP TIME READY
LTC1857/LTC1858/LTC1859
17
Figure 11. Wake Up from Sleep Mode for the LTC1859*
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
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SCK
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Figure 9. Nap Mode Operation for the LTC1859*
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CONVST
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LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 12 shows a typical SINAD of 87dB with a 100kHz sampling rate and a 1kHz input. TOTAL HARMONIC DISTORTION Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
V22 + V32 + V42 ... + VN2 THD = 20log V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15
MAGNITUDE (dB)
Figure 12. LTC1859 Nonaveraged 4096 Point FFT Plot
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BOARD LAYOUT, POWER SUPPLIES AND DECOUPLING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1857/LTC1858/LTC1859, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. In applications where the MUX is connected to the ADC, it is possible to get noise coupling into the ADC from the trace connecting the MUXOUT to the ADC. Therefore, reducing the length of the traces connecting the MUXOUT pins (Pins 10, 11) to the ADC pins (Pins 12, 13) can minimize the problem. The unused MUX inputs should be grounded to prevent noise coupling into the inputs. Figure 13 shows the power supply grounding that will help obtain the best performance from the 12-bit/14-bit/16-bit ADCs. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1857/
fSAMPLE = 100kHz fIN = 1kHz SINAD = 86.95dB THD = -101.42dB 30 20 25 FREQUENCY (kHz) 35 40 45 50
1859 F12
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185789f
LTC1857/LTC1858/LTC1859
APPLICATIO S I FOR ATIO
LTC1858/LTC1859 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference
+ -
LTC1857/ LTC1858/ CH0 LTC1859 10 12 CH1 MUXOUT + ADC+ CH2 LTC1857/LTC1858/LTC1859 CH3 CH4 ADC- MUXOUT - VREF REFCOMP AGND AVDD DVDD DGND 11 13 CH5 CH6 15 16 14, 17, 18 19 20 24 CH7 10F 10F 10F 1F COM
ANALOG GROUND PLANE
1859 F13
Figure 13. Power Supply Grounding Practice
PACKAGE DESCRIPTIO
G Package 28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.8 - 8.2
0.42 0.03 5.00 - 5.60** (.197 - .221) RECOMMENDED SOLDER PAD LAYOUT
0 - 8
0.09 - 0.25 (.0035 - .010)
0.55 - 0.95 (.022 - .037)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.22 - 0.38 0.05 (.009 - .015) (.002) TYP MIN *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
0.65 (.0256) BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the power supply ground connection.
DIGITAL SYSTEM OVDD 21 10F
1.25 0.12 5.3 - 5.7 0.65 BSC 2.0 (.079) MAX 9.90 - 10.50* (.390 - .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7.40 - 8.20 (.291 - .323) 1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 0204
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LTC1857/LTC1858/LTC1859
TYPICAL APPLICATIO
5V
AVDD 1 COM 2 CH0 SINGLE-ENDED OR DIFFERENTIAL CHANNEL SELECTION (SEE TABLE 1) INPUT RANGES: 0V TO 5V 0V TO 10V 5V AND 10V 3 CH1 INPUT MUX AND RANGE SELECT INTERNAL CLOCK MUX ADDRESS AND RANGE
* * *
9 CH7
AGND1
MUXOUT- 14 11
RELATED PARTS
PART NUMBER Sampling ADCs LTC1417 LTC1418 LTC1604 LTC1605 LTC1606 LTC1608 LTC1609 LTC1850/LTC1851 LTC1852/LTC1853 LTC1864/LTC1865 LTC1864L/LTC1865L DACs LTC1588/LTC1589 LTC1592 LTC1595 LTC1596 LTC1597 LTC1650 Op Amps LT1468/LT1469 DESCRIPTION 14-Bit, 400ksps Serial ADC 14-Bit, 200ksps, Single 5V or 5V ADC 16-Bit, 333ksps, 5V ADC 16-Bit, 100ksps, Single 5V ADC 16-Bit, 250ksps, Single 5V ADC 16-Bit, 500ksps, 5V ADC 16-Bit, 200ksps Serial ADC 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC 10-Bit/12-Bit, 8-Channel, 400ksps ADC 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP 12-/14-/16-Bit, Serial, SoftSpan IOUT DACs 16-Bit Serial Multiplying IOUT DAC in SO-8 16-Bit Serial Multiplying IOUT DAC 16-Bit Parallel, Multiplying DAC 16-Bit Serial VOUT DAC COMMENTS 5V or 5V, 20mW, 81dB SINAD and -95dB THD 15mW, Serial/Parallel I/O 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606 10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605 90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604 Configurable Unipolar/Bipolar Input, Single 5V Supply Programmable MUX and Sequencer, Parallel I/O Single 3V-5V, Programmable MUX and Sequencer, Parallel I/O Single 5V Supply, 850A with Autoshutdown Single 3V Supply, 450A with Autoshutdown Software-Selectable Spans, 1LSB INL/DNL 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors Low Power, Low Gritch, 4-Quadrant Multiplication
Single/Dual 90MHz, 22V/s, 16-Bit Accurate Op Amp Low Input Offset : 75V/125V
185789f LT/TP 0904 1K * PRINTED IN THE USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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5V 10F 19 0.1F 20 DVDD CONVST 28 CONTROL LOGIC SDI 25 BUSY 22 8-BIT SERIAL DATA INPUT 10F 0.1F SCK 26 16 SHIFT CLOCK CYCLES
+
12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O 4.096V 2.5V REFERENCE 1.6384X
RD 27 OVDD 21 10F SDO 23 16-BIT SERIAL DATA OUT 0.1F 3V TO 5V
-
8k MUXOUT+ 10 ADC+ 12 ADC- 13 VREF 15 1F 10F
REFCOMP 16 0.1F
AGND2 AGND3 DGND 17 18 24
1859 TA03
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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